Digital-to-analog converter

ABSTRACT

Embodiments of a digital-to-analog converter are disclosed.

CLAIM FOR PRIORITY

The current patent application claims priority to U.S. provisionalpatent application No. 60/639,085, filed on Dec. 23, 2004, titled“Methods for Shaping and Reduction of Digital-to-Analog ConverterNoise,” assigned to the assignee of the presently claimed subjectmatter.

FIELD

This disclosure is related to digital-to-analog converters.

BACKGROUND

Digital-to-analog converters, such as, for example, sigma-deltamodulators, are subject to errors and/or noise from a variety ofsources, including device mismatch.

BRIEF DESCRIPTION OF THE DRAWINGS

Subject matter is particularly pointed out and distinctly claimed in theconcluding portion of the specification. Claimed subject matter,however, both as to organization and method of operation, together withobjects, features, and advantages thereof, may best be understood byreference of the following detailed description if read with theaccompanying drawings in which:

FIG. 1 is a schematic diagram illustrating an embodiment of a k-bit DACwith dynamic element matching;

FIG. 2 is a schematic diagram illustrating an embodiment of a multi-bitsigma-delta ADC structure;

FIG. 3 is a schematic diagram illustrating an embodiment of asigma-delta ADC with spectrally shaping;

FIG. 4 is a schematic diagram illustrating an embodiment of asigma-delta modulator linear model;

FIG. 5 is a schematic diagram of an embodiment of a DAC with noiseshaping;

FIG. 6 is a plot of an output power spectral density of a fifth-order5-bit low-pass sigma-delta modulator with an internal DAC, fromsimulation;

FIG. 7 is a plot of an output power spectral density of a fifth-order5-bit low-pass sigma-delta modulator with an internal DAC having 2%mismatch, from simulation;

FIG. 8 is a plot of an output power spectrum density of a fifth-order5-bit low-pass sigma-delta modulator with an internal DAC having 2%mismatch, with an embodiment of spectral shaping applied, fromsimulation;

FIG. 9 is a plot of an output power spectral density of a sixth-order4-bit band-pass sigma-delta modulator with an internal DAC, fromsimulation;

FIG. 10 is a plot of an output power spectral density of a sixth-order4-bit band-pass sigma-delta modulator with an internal DAC having 2%mismatch, from simulation;

FIG. 11 is a plot of an output power spectral density of a sixth-order4-bit band-pass sigma-delta modulator with an internal DAC having 2%mismatch, with an embodiment of spectral shaping applied, from Matlabsimulation.

FIG. 12 is a schematic diagram of an embodiment of a multi-bitsigma-delta DAC structure; and

FIG. 13 is a schematic diagram of an embodiment of a sigma-delta DACwith spectral shaping.

DETAILED DESCRIPTION

Due at least in part to device mismatch, monolithic digital-to-analogconverters (DACs) may exhibit non-linear characteristics. Thus, atransfer characteristic or transfer function describing conversion froman digital to analog domain may be nonlinear. Such nonlinearities mayintroduce errors and/or result distortion of an analog signal and may,likewise, degrade performance of a DAC. Nonlinearity, together withother potential noise sources, such as thermal noise, for example, maybe considered noise generated inherently. In multi-bit sigma-deltamodulator, the digitized signal is converted back to analog domain inthe feedback path, typically through an internal DAC, and subsequentlysubtracted or offset from an input signal. If the feedback signalincludes noise, it may degrade performance of the sigma-delta modulator.Thus, advantage attributed to employing multi-bit quantization may bereduced.

Several methods have been proposed to address this issue. They may bedivided at a high level into two categories. One may be referred to asan element calibration approach and the other may be referred to as aDynamic Element Matching (DEM) technique.

In the first category, different methods may be employed depending atleast in part on implementation of the DAC. For example, resistorelements may be laser-trimmed in the fabrication, but this may raisecost of manufacture. Current sources may be calibrated by changing thegate voltage or by combining coarse DAC with a fine DAC for calibration.Capacitors may be trimmed by switching in small additional capacitors.However, typically, this method incurs additional chip fabrication cost.In addition, both factory-trimming and calibration at startup may alsosuffer from element matching variations associated with, for example,age and temperature changes. Periodical or continuous backgroundcalibration may be employed; however, circuit complexity and cost may befurther increased.

The second category may be referred to as Dynamic Element Matching(DEM). With DEM, integral and differential linearity may be achieved,with modest matching of the components.

The principle is illustrated in FIG. 1. A binary input-code of a DAC istransformed into a thermometer-code of 2^(k−1) lines. In a DAC withoutDEM, these bit lines control one specific unit element of the DAC. Dueat least in part to fabrication process variations, the values of theseunit elements may not be equal and may introduce nonlinearity errors. IfDEM is employed, this one-to-one correspondence may be broken by theelement selection block. Hence, the element selecting block selectsdifferent unit elements to represent a certain input code. Instead ofhaving a fixed error for this certain input code, in a clock period atime-varying error signal may result. For example, some of the unitelements may have a positive contribution to the error, while others mayhave a negative contribution. The element selection logic may make thistime-varying error signal to average to close to zero over multipleclock periods. The averaged output signal may therefore approaches anideal output signal. In other words, errors due to component mismatchare “whitened” in a wide frequency band or moved out of signal band.Therefore, error may be removed by filtering, such as via oversampling.An averaged output signal may be a few orders of magnitude better.

An advantage of DEM is that it may work without specific knowledge ofthe actual mismatch of the unit elements, in contrast to calibrationtechniques that employ an exact measurement to compensate for errors.Therefore, DEM is, in general, less sensitive to matching variationattributable to age and temperature, for example.

A sigma-delta modulator employing DEM DAC was first reported in L. R.Carley and J. Kenney, “A 16-bit 4^(th) order noise-shaping D/A conver”,in Proceeding Custom Integrated Circuit Conference, June 1988, pp.21.7.1-21.7.4; and L. R. Carley, “A noise-shaping coder topology for 15+bit converters”, IEEE Journal of Solid-State Circuits, vol. 28, no, 2,pp. 267-273, Apr. 1989. A three-stage eight-line butterfly randomizer isused to randomly select unit elements. The dc-error and harmonicdistortion components in this modulator are spread across the frequencyband. Thus, the tone related noise power is reduced, but the noise flooris increased. From applying DEM DAC tp sigma-delta modulation, thesignal-to-noise-and-distortion Ratio (SNDR) is improved while thesignal-to-noise Ratio (SNR) is degraded due to the increased noisefloor.

Another approach to DEM is the Data Weighted Averaging (DWA). DWA triesto have the elements used with substantially equal probability for adigital input code. This is done by sequentially selection elements froman array, beginning with the next available unused element. Usingelements at a relatively high rate may assist in having DAC errorsquickly average to zero, moving distortion to high frequencies. It hasbeen demonstrated that DWA provides first-order shaping of the DACnonlinear error. A digital dither is employed to whiten the noise sothat it may be shaped.

Some modified DWA approaches have also bee proposed, among them are theincremental DWA (IDWA), DWA with rotated cycles, and bi-directional dataweighted averaging (biDWA). In IDWA, m extra unit elements are added tothe DAC such that during a clock cycle at least k unit elements are notused. In this method, the drop in performance near 0.01V_(REF) isremoved. However, a drop in the SNDR curve now occurs for larger inputamplitudes. This shows that the location of the tones is difficult toaccurately controlled and in-band tones may still occur. In DWA withrotated cycles, the element access cycles rotate through the elementssimilar to DWA, but occasionally changes the sequence of the elements.This results in the removal of the tones. However, if te sequence ischanged too frequently, performance will be degraded. The hardwareimplementation for this method is complex. BiDWA is a modified versionof DWA. It uses two pointers, one for the even clock cycles and theother for the odd. While the even clock cycles rotate the used elementsin one direction, the odd clock cycles rotates in the other direction,unlike DWA that empoys one direction pointer. Compared to DWA, biDWAinvolves more hardware. The in-band DAC error of biDWA is larger thanthat of DWA, but the biDWA's DAC error contains no tones or peaks. Thisresults in a worse SNR and SNDR, but a slightly better Spurious FreeDynamic Range (SFDR). BiDWA also suffers from variations of the DACerror versus the signal amplitude similar to DWA.

A second-order low-pass DEM technique, referred to as DWA 02, has alsobeen proposed. This technique has some unit elements contribute multipletimes in one clock cycle. To implement this, the clock period is dividedinto sub-periods. In a sub-period, a specific unit element may haveeither a positive, negative or zero contribution. Since contributions ofthe different elements involve a certain time to be integrated withinthe desired accuracy, the maximum clock speed of the converter may bedegraded. Therefore, this technique is typically not suitable for highspeed converters. However, it offers a performance improvement over DWAin low speed sigma-delta modulators. The in-band DAC error is typicallysmaller than that of DWA due to the second-order shaping.

Another DEM approach uses a tree-structure to perform the shufflingoperation of the selected unit elements of DAC. The tree-structure for aDAC comprises unit elements and a “tree” shaped switching network formedby multiple sub-switching blocks and used to select these unit elements.A sub-switching block may include a high-pass noise shaping function togenerate a control signal for subsequent switching blocks in thenetwork. Therefore, different shaped DAC errors may be achieved byemploying different high-pass noise shaping functions, such as first-and second-order noise shaping. The first-order noise shaping with thetree-structure shows similar characteristics and comparable performanceas DWA. However, DWA is typically preferred due to less complex hardwarefor implementation. The second-order noise shaping may potentially beoverloaded for large input signals. If overload occurs, second-ordernoise-shaped DAC can no longer obtained usually.

In summary, DWA seems to offer good performance if DAC nonlinearityerror is first-order shaped. Due to its simplicity, it includes anadvantage of a small amount of hardware overhead and being suitable forhigh speed converter. A drawback of DWA is performance degradation ifthe input signal is near 0.01V_(REF). Although this potentiallyaddressed by modified DWA approaches, it usually involves increasedhardware complexity.

These DEM approaches are limited in shaping the DAC nonlinearity errorat low frequency and, therefore, are typically limited to low-passsigma-delta ADC. Furthermore, these approaches do not address inherentDAC noise other than nonlinearity, such as thermal noise, for example.

FIG. 2 is a schematic diagram illustrating a multi-bit sigma-deltaanalog-to-digital conversion (ADC) structure. Multi-bit i DAC 4 convertsthe digital output signal of quantizer 2 to an analog signal. Thisanalog signal may be subtracted from the input signal and passes througha loop filter 1. Quantization noise generated by quantizer 2 may beshaped out of the signal band. However, the DAC noise cannot be shapedand may corrupt the sigma-delta input signal. Hence, the dynamic rangeof the sigma-delta modulator may be reduced.

FIG. 3 is a schematic diagram illustrating an embodiment of a possiblearchitecture for a sigma-delta modulator. In FIG. 3, two signalprocessing blocks, 7 and 10, are inserted in the front of a randomizingelement selection logic block 8 and after DAC block 9, respectively.HD(z) 10 is used to shape DAC noise out of signal band. The zeros ofHD(z) 10 should be located in the signal band to reduce the in band DACnoise. HI(z) 7 in the digital domain is used to counteract the functionof HD(z) 10 in the analog domain. Hence, the modulator output signal maybe feedback through DAC 9 without being changed by these additionalblocks. Such an embodiment may be employed in low-pass or band-passsigma-delta modulators by shifting the zeros of HD(z) 10 to the signalband of interest. High-orders of HI(z) 7 and HD(z) 10 may also beemployed for better noise shaping effect.

If DAC nonlinearity error is whitened by randomly selecting the DACelement, a linear model of a sigma-delta modulator may be derived, suchas illustrated in FIG. 4, for example. The noise of quantizer 12 and DAC14, shown here as Q(z) and D(z), are modelled as additive white noise.

For example, the transfer function of the modulator may be expressed asfollows:${V(z)} = {{\frac{H(z)}{1 + {{H(z)}{{HI}(z)}{{HD}(z)}}}{U(z)}} + {\frac{1}{1 + {{H(z)}{{HI}(z)}{{HD}(z)}}}{Q(z)}} - {\frac{{H(z)}{{HD}(z)}}{1 + {{H(z)}{{HI}(z)}{{HD}(z)}}}{D(z)}}}$

Likewise, the transfer function of signal U(z) may be expressed as:$H_{s} = \frac{H(z)}{1 + {{H(z)}{{HI}(z)}{{HD}(z)}}}$

The transfer function of the quantization error may be expressed as:$H_{Q} = \frac{1}{1 + {{H(z)}{{HI}(z)}{{HD}(z)}}}$

Likewise, the noise transfer function for the DAC may be expressed as:$H_{D} = \frac{{- {H(z)}}{{HD}(z)}}{1 + {{H(z)}{{HI}(z)}{{HD}(z)}}}$

If HI(z) 7 and HD(z) 10 cancelled one another, HI(z)HD(z)=1.

Thus, the previous expressions may be rewritten as:${V(z)} = {{\frac{H(z)}{1 + {H(z)}}{U(z)}} + {\frac{1}{1 + {H(z)}}{D(z)}} - {\frac{{H(z)}{{HD}(z)}}{1 + {H(z)}}{E(z)}}}$$H_{s} = \frac{H(z)}{1 + {H(z)}}$ $H_{Q} = \frac{1}{1 + {H(z)}}$$H_{D} = \frac{{- {H(z)}}{{HD}(z)}}{1 + {H(z)}}$For low-pass sigma-delta ADC, high-pass noise shaping may be applied.Thus, HD(z) may comprise a differentiator, such as one with a transferfunction, for example, as:HD _(lp)(z)=1−z ⁻¹To substantially offset HD(z), HI(z) may comprise an accumulator, suchas one with a transfer function, for example, as:${{HI}_{lp}(z)} = \frac{1}{1 - z^{- 1}}$Here resulting noise shaping is of first order. For simplicity, the zeroof HD(z) is placed at dc, though it may be spread to the center of thesignal band for better noise shaping effect, for example. FIG. 5illustrates DAC noise spectrally shaped by such a differentiator forthis particular embodiment, although, claimed subject matter is notlimited in scope to this example or embodiment, of course.

Simulation has been employed to model an embodiment in accordance withclaimed subject matter. For example, a multi-bit fifth-order low-passsigma-delta modulator with a 5-bit quantizer and 8-bit DAC is used as anexample, although, of course, claimed subject matter is not limited inscope to this particular example. FIG. 6 shows a plot of an output powerspectral density (PSD) with a DAC produced by simulation. FIG. 7 a plotof the output PSD with a DAC where 2% mismatch has been included. FIG. 8shows a plot of the output PSD with the DAC having 2% mismatch, but inwhich an embodiment of spectral shaping has also been applied. Again,these plots were generated by simulation. Inspection of these plotsillustrates performance improvement.

In a situation involving band-pass which a sampling frequency of 4 timesof a signal center frequency, f_(s)=4 f₀, is employed, a transferfunction may be obtained by substituting z with −z² with respect toHD_(lp) and HI_(lp) in the above mentioned low-pass example.

The resulting HD(z) and HI(z) may be expressed as follows:${{HI}_{bp}(z)} = {{\frac{1}{1 + z^{- 2}}\quad{and}\quad{{HD}_{bp}(z)}} = {1 + z^{- 2}}}$Simulation results, for a multi-bit sixth-order band-pass sigma-deltaADC with a 4-bit quantizer and a DAC with DEM, are shown in FIGS. 9 to11. FIG. 9 shows an output power spectral density (PSD) with a DAC. FIG.10 shows an output PSD with a DAC having 2% mismatch. FIG. 11 shows anoutput PSD with a DAC having 2% mismatch, but spectrally shaped via anembodiment in accordance with claimed subject matter.

In an alternate embodiment, spectral shaping may also be applied to asigma-delta DAC. FIG. 13 shows an embodiment of a sigma-delta DAC withan embodiment of a noise shaping DAC. HD(z) 22 may be used to shape theDAC noise out of signal band, while HI(z) 19 may be used to offset thefunction of HD(z), so that the output signal of the DAC would notsignificantly be affected by the additional blocks, here HD(z) andHI(z). For comparison, FIG. 12 illustrates a multi-bit sigma-delta DACwithout these components.

1. An apparatus comprising: a digital-to-analog converter (DAC); saidDAC having a feedback path that includes an accumulator to employspectral shaping in connection with dynamic element matching and adifferentiator to substantially offset said accumulator.
 2. Theapparatus of claim 1, wherein said DAC comprises a sigma-deltamodulator.
 3. The apparatus of claim 2, wherein said sigma-deltamodulator comprises a multi-bit sigma-delta modulator.
 4. The apparatusof claim 1, wherein said DAC comprises a low-pass DAC.
 5. The apparatusof claim 1, wherein said DAC comprises a band-pass DAC.
 6. The apparatusof claim 1, wherein said DAC comprises a high-pass DAC.
 7. An apparatuscomprising: a digital-to-analog converter (DAC); said DAC having afeedback path comprising means for applying spectral shaping to dynamicelement matching and means for substantially offsetting said spectralshaping.
 8. The apparatus of claim 7, wherein said DAC comprises asigma-delta modulator.
 9. A method comprising: spectrally shaping asignal prior to application to randomizing logic; and substantiallyoffsetting the spectral shaping prior to application of said signal asfeedback.
 10. The method of claim 9, wherein said randomized logic isemployed to perform dynamic element matching for a digital-to-analogconverter.
 11. The method of claim 9, wherein said spectral shapingcomprises an order higher than one.
 12. The method of claim 11, whereinsaid order higher than one comprises an order higher than two.
 13. Alowpass sigma-delta modulator comprising: a summing circuit forreceiving an input and a feedback signal and producing an output; a loopfilter receiving the output of said summing circuit as an input andproducing an output; a quantizer receiving the output of said loopfilter and producing an N-bit digital output which is the output of saidmodulator, N being an integer with a value greater than one; a digitalintegrator receiving the output of said quantizer as an input andproducing an output; a randomizer block receiving the output of saiddigital integrator as an input and produce an output; adigital-to-analog converter receiving said output of said randomizerblock as an input and producing an output; an analog differentiatorreceiving the output of said digital-to-analog converter as an input andproducing said feedback signal.
 14. A lowpass sigma-delta modulatorcomprising: a summing circuit for receiving an input and a feedbacksignal and producing an output; a loop filter receiving the output ofsaid summing circuit as an input and producing an output; a quantizerreceiving the output of said loop filter and producing an N-bit digitaloutput which is the output of said modulator, N being an integer with avalue greater than one; a digital L^(th)-order lowpass filter receivingthe output of said quantizer as an input and producing an output, Lbeing an integer with a value greater than zero; a randomizer blockreceiving the output of said digital L^(th)-order lowpass filter as aninput and produce an output; a digital-to-analog converter receivingsaid output of said randomizer block as an input and producing anoutput; an analog L^(th)-order highpass filter receiving the output ofsaid digital-to-analog converter as an input and producing said feedbacksignal, L being an integer with a value greater than zero.
 15. Abandpass sigma-delta modulator comprising: a summing circuit forreceiving an input and a feedback signal and producing an output; a loopfilter receiving the output of said summing circuit as an input andproducing an output; a quantizer receiving the output of said loopfilter and producing an N-bit digital output which is the output of saidmodulator, N being an integer with a value greater than one; a digitalL^(th)-order bandpass filter receiving the output of said quantizer asan input and producing an output, L being an integer with a valuegreater than zero; a randomizer block receiving the output of saiddigital L^(th)-order bandpass filter as an input and produce an output;a digital-to-analog converter receiving said output of said randomizerblock as an input and producing an output; an analog L^(th)-order bandrejection filter receiving the output of said digital-to-analogconverter as an input and producing said feedback signal, L being aninteger with a value greater than zero.
 16. The sigma-delta modulator ofclaim 15, wherein said loop filter can be realized in eitherdiscrete-time or continuous-time circuits.
 17. A lowpass sigma-deltadigital-to-analog converter comprising: an interpolation filter forreceiving an input and producing an output; a summing circuit forreceiving the output of said interpolation filter and a feedback signaland producing an output; a loop filter receiving the output of saidsumming circuit as an input and producing an output; a truncatorreceiving the output of said loop filter and producing said feedbacksignal, an N-bit truncated digital signal, N being an integer with avalue greater than one; a digital integrator receiving the output ofsaid truncator as an input and producing an output; a randomizer blockreceiving the output of said digital integrator as an input and producean output; a digital-to-analog converter receiving said output of saidrandomizer block as an input and producing an output; an analogdifferentiator receiving the output of said digital-to-analog converteras an input and producing an output; an analog post filter receiving theoutput of said analog differentiator and producing the output of saidlowpass sigma-delta digital-to-analog converter.
 18. A lowpasssigma-delta digital-to-analog converter comprising: an interpolationfilter for receiving an input and producing an output; a summing circuitfor receiving the output of said interpolation filter and a feedbacksignal and producing an output; a loop filter receiving the output ofsaid summing circuit as an input and producing an output; a truncatorreceiving the output of said loop filter and producing said feedbacksignal, an N-bit truncated digital signal, N being an integer with avalue greater than one; a digital L^(th)-order lowpass filter receivingthe output of said truncator as an input and producing an output, Lbeing an integer with a value greater than zero; a randomizer blockreceiving the output of said digital L^(th)-order lowpass filter as aninput and produce an output; a digital-to-analog converter receivingsaid output of said randomizer block as an input and producing anoutput; an analog L^(th)-order highpass filter receiving the output ofsaid digital-to-analog converter as an input and producing an output, Lbeing an integer with a value greater than zero; an analog post filterreceiving the output of said analog L^(th)-order highpass filter andproducing the output of said lowpass sigma-delta digital-to-analogconverter.
 19. A bandpass sigma-delta digital-to-analog convertercomprising: an interpolation filter for receiving an input and producingan output; a summing circuit for receiving the output of saidinterpolation filter and a feedback signal and producing an output; aloop filter receiving the output of said summing circuit as an input andproducing an output; a truncator receiving the output of said loopfilter and producing said feedback signal, an N-bit truncated digitalsignal, N being an integer with a value greater than one; a digitalL^(th)-order bandpass filter receiving the output of said truncator asan input and producing an output, L being an integer with a valuegreater than zero; a randomizer block receiving the output of saiddigital L^(th)-order bandpass filter as an input and produce an output;a digital-to-analog converter receiving said output of said randomizerblock as an input and producing an output; an analog L^(th)-order bandrejection filter receiving the output of said digital-to-analogconverter as an input and producing an output, L being an integer with avalue greater than zero; an analog post filter receiving the output ofsaid analog L^(th)-order band rejection filter and producing the outputof said bandpass sigma-delta digital-to-analog converter.